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| PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT PD46128512-X 128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION Description The PD46128512-X is a high speed, low power, 134,217,728 bits (8,388,608 words by 16 bits) CMOS Mobile Specified RAM featuring asynchronous page read and random write, synchronous burst read/write function. The PD46128512-X is fabricated with advanced CMOS technology using one-transistor memory cell. Features * 8,388,608 words by 16 bits organization * Asynchronous page read mode * Synchronous read and write mode * Burst length: 8 words / 16 words / continuous * Clock latency: 5, 6, 7, 8, 9, 10 * Burst sequence: Linear burst * Max clock frequency: 108/83 MHz * Byte data control: /LB (DQ0 to DQ7), /UB (DQ8 to DQ15) * Low voltage operation: 1.7 to 2.0 V * Operating ambient temperature: TA = -30 to +85 C * Chip Enable input: /CE1 pin * Standby Mode input: CE2 pin * Standby Mode 1: Normal standby (Memory cell data hold valid) * Standby Mode 2: Density of memory cell data hold is variable PD46128512 Clock frequency MHz (MAX.) Asynchronous Operating initial access time ns (MAX.) supply voltage V Operating ambient temperature C At operating mA (MAX.) (MAX.) Density of data hold 128M 32M bits -E9X Note Note Supply current At standby A (TYP.) Density of data hold 0M bits 65 128M 32M bits 80 bits 16M bits 8M bits 0M bits 15 16M bits 8M bits bits 108 70 85 1.7 to 2.0 -30 to +85 60 50 60 50 250 T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. -E10X -E11X -E12X 83 70 85 Note Under consideration The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M17507EJ2V0DS00 (2nd edition) Date Published September 2005 CP (K) Printed in Japan The mark shows major revised points. 2005 PD46128512-X Ordering Information PD46128512-X is mainly shipping by wafer. Please consult with our sales offices for package samples and ordering information. 2 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Pin Configuration The following is pin configuration of package sample. /xxx indicates active low signal. 93-PIN TAPE FBGA (12x9) Top View Bottom View 10 9 8 7 6 5 4 3 2 1 A BCDE FGH J K LM N P PNM L K J HGF EDCBA Top View A 10 9 8 7 6 5 4 3 2 1 NC NC NC NC NC NC NC NC NC B NC NC C NC NC NC A11 A8 /WE CLK /LB A7 NC A15 A12 A19 CE2 /ADV /UB A6 A3 A21 A13 A9 A20 /WAIT A18 A5 A2 D E F G NC A22 A14 A10 NC NC A17 A4 A1 NC H NC A16 NC DQ6 NC NC DQ1 GND A0 NC NC DQ15 DQ13 DQ4 DQ3 DQ9 /OE NC Vss DQ7 DQ12 VCC VCC DQ10 DQ0 /CE1 DQ14 DQ5 NC DQ11 DQ2 DQ8 NC NC NC NC NC NC NC NC J K L M NC NC NC N NC NC P NC A0 to A22 /CE1 CE2 /WE /OE /LB, /UB : Address inputs : Chip select input : Standby mode input : Write enable input : Output enable input : Byte data select input CLK /ADV /WAIT VCC GND NC Note : Clock input : Address Valid Input : Wait output : Power supply : Ground : No Connection DQ0 to DQ15 : Data inputs / outputs Note Some signals can be applied because this pin is not internally connected. Remark Refer to Package Drawing for the index mark. Preliminary Data Sheet M17507EJ2V0DS 3 PD46128512-X Block Diagram Standby mode control VCC VCCQ GND Refresh counter A0 to A22 CLK /ADV DQ0 to DQ7 DQ8 to DQ15 Address buffer Row decoder Refresh control Memory cell array 134,217,728 bits Address latch Sense amplifier / Switching circuit Column decoder Input data controller Output data controller /WAIT Internal state control /CE1 CE2 /LB /UB /WE /OE 4 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Truth Table Asynchronous Operation Mode /CE1 CE2 /ADV /OE /WE /LB /UB DQ DQ0 to DQ7 DQ8 to DQ15 Not selected (Standby Mode 1) Not selected (Standby Mode 2) Word read Lower byte read Upper byte read Output disable Output disable Word write Lower byte write Upper byte write Abort write Note2 Note1 /WAIT H x L H L H x x Note3 x x L x x H x x L L H H x x L H L H x L H L H High-Z High-Z DOUT DOUT High-Z High-Z High-Z DIN DIN High-Z High-Z High-Z High-Z DOUT High-Z DOUT High-Z High-Z DIN High-Z DIN High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z H L x L L H H Notes 1. 3. CE2 pin must be fixed HIGH except Standby Mode 2 (refer to 2.3 Standby Mode Status Transition). Fixed LOW or toggle HIGH LOW HIGH 2. If /WE = LOW and /LB = /UB = HIGH, memory does not accept write data, so write operation is not available. Remark H, HIGH : VIH, L, LOW : VIL, x: VIH or VIL Clock pin must be fixed either LOW or HIGH. Preliminary Data Sheet M17507EJ2V0DS 5 PD46128512-X Burst Operation Mode /CE1 CE2 CLK /ADV /OE /WE /LB /UB DQ DQ0 to DQ7 Not selected (Standby Mode 1) Not selected (Standby Mode 2) Start address latch Advanced burst read to next address Note4 Note1 /WAIT Note8 DQ8 to DQ15 High-Z High-Z High-Z Note5 DOUT H x L H L H x x Note4 x x L H x x x Note7 L x x x Note7 H x x x Note9 x x x Note9 High-Z High-Z High-Z Note5 DOUT High-Z High-Z x Output Valid Burst read suspend Burst read resume Note2 H L x L Note4 High-Z DOUT High-Z L DIN High-Z DOUT High-Z DIN HIGH HIGH High-Z Output Valid Note2 Burst read termination Note3 Advanced burst write to next address x H Burst write suspend Burst write resume Note2 H L x L x x x Note10 High-Z DIN High-Z HIGH HIGH High-Z High-Z DIN High-Z High-Z HIGH HIGH High-Z HIGH Note2 Burst write termination Note3 Abort write Note6 Notes 1. 2. CE2 pin must be fixed HIGH except Standby Mode 2 (refer to 2.3 Standby Mode Status Transition). Be sure to suspend or resume a burst read after outputting the first read access data. Be sure to suspend or resume a burst write after latching the first write data. Burst write suspend or resume is available when setting WC = 1 (/WE level control) through Mode Register Set. 3. 4. 5. /CE1 must be fixed HIGH during tTRB specification until next read or write operation. Valid clock edge shall be set either positive or negative edge through Mode Register Set. If /OE = LOW and /LB = /UB = LOW, output is valid. If /OE = LOW and /LB = /UB = HIGH, output is high impedance. If /WE = LOW, output is high impedance. If /OE = /WE = HIGH, output is high impedance. 6. 7. 8. 9. If /WE = LOW and /LB = /UB = HIGH, memory does not accept write data, so write operation is not available. Both of two pins (/OE and /WE) or either of two should be connected to HIGH. It is prohibited to bring the both /OE and /WE to LOW. Refer to the 4.10 /WAIT. For the Burst Read, the /UB, /LB setup time to CLK (tBC) must be satisfied. For the Burst Write, the /UB, /LB setup time to CLK (tBC) must be satisfied. Once /LB and /UB inputs are determined, they must not be changed until the end of burst operation. 10. In case of WC = 0, /WE is HIGH. In case of WC = 1, /WE is LOW. The explanation of WC refers to Table 5-2. Mode Register Definition (5th Bus Cycle) and 5.9 /WE control. Remark H, HIGH : VIH, L, LOW : VIL, x: VIH or VIL, : valid edge 6 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X CONTENTS 1. Initialization .................................................................................................................................................. 9 2. Partial Refresh ........................................................................................................................................... 11 2.1 Standby Mode.......................................................................................................................................................... 11 2.2 Density Switching .................................................................................................................................................... 11 2.3 Standby Mode Status Transition.............................................................................................................................. 11 2.4 Addresses for Which Partial Refresh Is Supported.................................................................................................. 13 3. Page Read Operation ................................................................................................................................ 14 3.1 Features of Page Read Operation ........................................................................................................................... 14 3.2 Page Length ............................................................................................................................................................ 14 3.3 Page-Corresponding Addresses.............................................................................................................................. 14 3.4 Page Start Address.................................................................................................................................................. 14 3.5 Page Direction ......................................................................................................................................................... 14 3.6 Interrupt during Page Read Operation..................................................................................................................... 14 3.7 When Page Read is not Used.................................................................................................................................. 14 4. Burst Operation ......................................................................................................................................... 15 4.1 Features of Burst Operation .................................................................................................................................... 15 4.2 Burst Length ............................................................................................................................................................ 15 4.3 Latency .................................................................................................................................................................... 15 4.4 Single Write ............................................................................................................................................................. 17 4.5 /WE Control ............................................................................................................................................................. 17 4.6 Burst Read Suspend/Resume ................................................................................................................................. 18 4.7 Burst Write Suspend/Resume ................................................................................................................................. 19 4.8 Burst Read Termination........................................................................................................................................... 20 4.9 Burst Write Termination ........................................................................................................................................... 21 4.10 /WAIT..................................................................................................................................................................... 22 4.10.1 Feature of /WAIT Output ............................................................................................................................. 22 4.10.2 Dummy Wait Cycles at Continuous Burst Operation ................................................................................... 25 4.11 Reset Function from Synchronous Burst Mode to Asynchronous Page Mode....................................................... 27 5. Mode Register Settings............................................................................................................................. 28 5.1 Mode Register Setting Method ................................................................................................................................ 28 5.2 Cautions for Setting Mode Register ......................................................................................................................... 28 5.3 Partial Refresh Density ............................................................................................................................................ 30 5.4 Burst Length ............................................................................................................................................................ 30 5.5 Function Mode ......................................................................................................................................................... 30 5.6 Valid Clock Edge ..................................................................................................................................................... 30 5.7 Read Latency (Write Latency) ................................................................................................................................. 30 5.8 Single Write ............................................................................................................................................................. 30 5.9 /WE Control ............................................................................................................................................................. 31 5.10 Reset to Page Mode .............................................................................................................................................. 31 5.11 Reserved Bits ........................................................................................................................................................ 31 5.12 Cautions for Timing Chart of Setting Mode Register.............................................................................................. 32 6. Electrical Specifications ........................................................................................................................... 33 Preliminary Data Sheet M17507EJ2V0DS 7 PD46128512-X 7. Asynchronous AC Specification, Timing Chart ..................................................................................... 36 8. Synchronous AC Specification, Timing Chart........................................................................................ 57 9. Mode Register Setting Timing.................................................................................................................. 74 10. Standby Mode Timing Chart................................................................................................................... 77 11. Package Drawing..................................................................................................................................... 78 12. Recommended Soldering Conditions ................................................................................................... 79 8 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X 1. Initialization Initialize the PD46128512-X at power application using the following sequence to stabilize internal circuits. There are 2 method of initialization. Initialization Timing 1 (1) Following power application, make CE2 HIGH after fixing CE2 to LOW for the period of tVHMH. Make /CE1 HIGH before making CE2 HIGH. (2) /CE1 and CE2 are fixed HIGH for the period of tMHCL. Normal operation is possible after the completion of initialization. Figure 1-1. Initialization Timing Chart 1 Intialization Nomal Operation /CE1 (Input) tCHMH tVHMH CE2 (Input) tMHCL VCC, VCCQ VCC (MIN.), VCCQ (MIN.) Cautions 1. 2. Make CE2 LOW when starting the power supply. tVHMH is specified from when the power supply voltage reaches the prescribed minimum value (VCC (MIN.), VCCQ (MIN.)). Initialization Timing 1 Parameter Power application to CE2 LOW hold /CE1 HIGH to CE2 HIGH Following power application CE2 HIGH hold to /CE1 LOW Symbol tVHMH tCHMH tMHCL MIN. 50 0 300 MAX. Unit s ns s Preliminary Data Sheet M17507EJ2V0DS 9 PD46128512-X Initialization Timing 2 (1) Following power application, make CE2 and /CE1 HIGH for the period of tMHCL. Normal operation is possible after the completion of initialization. Figure 1-2. Initialization Timing Chart 2 Intialization Nomal Operation /CE1 (Input) tMHCL CE2 (Input) VCC, VCCQ VCC (MIN.), VCCQ (MIN.) Cautions 1. 2. tMHCL is specified from when the power supply voltage reaches the prescribed minimum value (VCC (MIN.), VCCQ (MIN.)). If the period from power supplying to value VCC (MIN.), VCCQ (MIN.) is beyond 10 ms or power supply is not stable rise, should be used Initialization Timing Chart 1. Initialization Timing 2 Parameter Following power application /CE1, CE2 HIGH hold to /CE1 LOW Symbol tMHCL MIN. 300 MAX. Unit s 10 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X 2. Partial Refresh 2.1 Standby Mode In addition to the regular standby mode (Standby Mode 1) with a 128M bits density, Standby Mode 2, which performs partial refresh, is also provided. 2.2 Density Switching In Standby Mode 2, the densities that can be selected for performing refresh are 32M bits, 16M bits, 8M bits, and 0M bit. The density for performing refresh can be set with the mode register. Once the refresh density has been set in the mode register, these settings are retained until they are set again, while applying the power supply. However, the mode register setting will become undefined if the power is turned off, so set the mode register again after power application. (For how to perform mode register settings, refer to section 5. Mode Register Settings.) 2.3 Standby Mode Status Transition In Standby Mode 1, /CE1 and CE2 are HIGH. In Standby Mode 2, CE2 is LOW. In Standby Mode 2, if 0M bit is set as the density, it is necessary to perform initialization the same way as after applying power, in order to return to normal operation from Standby Mode 2. When the density has been set to 32M bits, 16M bits, or 8M bits in Standby Mode 2, it is not necessary to perform initialization to return to normal operation from Standby Mode 2. For the timing charts, refer to Figure 10-1. Standby Mode 2 Entry / Exit Timing Chart (Asynchronous Mode), Figure 10-2. Standby Mode 2 (data not held) Entry / Exit Timing Chart (Asynchronous Mode). Preliminary Data Sheet M17507EJ2V0DS 11 12 Figure 2-1. Standby Mode State Machine Power On Mode Register Setting Initialize Note Initialize Burst Mode Page Mode /CE1 = VIH, CE2 = VIH Page Mode Standby Mode1 /CE1 = VIH, CE2 = VIL /CE1 = VIH, CE2 = VIH /CE1 = VIH, CE2 = VIL (RP=0) Standby Mode1 Burst Mode Preliminary Data Sheet M17507EJ2V0DS /CE1 = VIL, CE2 = VIH /CE1 = VIH, CE2 = VIL /CE1 = VIH, CE2 = VIL (RP=0) /CE1 = VIL, CE2 = VIH /CE1 = VIH, CE2 = VIL (RP=1) /CE1 = VIH, CE2 = VIL (RP=1) /CE1 = VIH, CE2 = VIH /CE1 = VIH, CE2 = VIH /CE1 = VIH, CE2 = VIH /CE1 = VIH, CE2 = VIH Active CE2 = VIL CE2 = VIL (RP=0) Standby Mode2 (32Mbit/16Mbit/8Mbit) Active CE2 = VIL (RP=1) Standby Mode2 (32Mbit/16Mbit/8Mbit) CE2 = VIL (RP=0) CE2 = VIL (RP=1) CE2 = VIL Standby Mode2 (Data not held) Standby Mode2 (Data not held) PD46128512-X Note Case "Initialization Timing 2" : Following initialization, set mode register. PD46128512-X 2.4 Addresses for Which Partial Refresh Is Supported Data hold density 32M bits 16M bits 8M bits Correspondence address 000000H to 1FFFFFH 000000H to 0FFFFFH 000000H to 07FFFFH Preliminary Data Sheet M17507EJ2V0DS 13 PD46128512-X 3. Page Read Operation For the timing charts, refer to Figure 7-10. Asynchronous Page Read Cycle Timing Chart. 3.1 Features of Page Read Operation Features Page length Page read-corresponding addresses Page read start address Page direction Interrupt during page read operation 16 words A3, A2, A1, A0 Don't care Don't care Enabled Note Item Note /CE1 = HIGH, or any change in address A4 or higher will initiate a new read access specified as tAA or tACE. 3.2 Page Length 16 words is supported as the page lengths. Page length is not necessary to set through Mode Register. 3.3 Page-Corresponding Addresses The 16 words page read-enabled addresses are A3, A2, A1, and A0. Fix addresses other than A3, A2, A1, and A0 during page read operation. 3.4 Page Start Address Since random page read is supported, any address (A3, A2, A1 and A0 with the 16 words page) can be used as the page read start address. 3.5 Page Direction Since random page read is possible, there is not restriction on the page direction. 3.6 Interrupt during Page Read Operation When generating an interrupt during page read, make /CE1 HIGH or change A4 and higher addresses. 3.7 When Page Read is not Used Since random page read is supported, even when not using page read, random access is possible as usual. 14 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X 4. Burst Operation Burst operation is valid when burst mode is set through mode register. 4.1 Features of Burst Operation Function Burst Length Read Latency Write Latency Burst Sequence Single Write Valid Clock Edge 8, 16, Continuous 5, 6, 7, 8, 9, 10 4, 5, 6, 7, 8, 9 Linear Single Write, Burst Write Rising Edge, Falling Edge Features 4.2 Burst Length Burst length is the number of word to be read or written during synchronous burst read/write operation as the result of a single address latch cycle. It can be set on 8, 16words boundary or continuous for entire address through Mode Register Set sequence. Starting from initial address being latched, device internal address counter assign +1 to the previous address until reaching the end of boundary address. After completing read data out or write data latch for the set burst length, operation automatically end except for continuous burst. When continuous burst length is set, read /write is endless unless it is terminated by the rising edge of /CE1. 4.3 Latency Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming available during synchronous burst read operation. It is set through Mode Register Set sequence after power application. Once RL is set through Mode Register Set sequence, write latency, that is the number of clock cycles between address being latched and first write data being latched, is automatically set to RL-1. Latency Count Grade Clock Frequency -E9X -E10X -E9X, -E11X -E10X, -E12X -E9X, -E11X -E10X, -E12X -E9X, -E11X -E10X, -E12X <52 MHz <66 MHz <83 MHz <108 MHz Asynchronous access time 70 ns 85 ns 70 ns 85 ns 70 ns 85 ns 70 ns 85 ns 8, 9, 10 10 7, 8, 9, 10 8, 9, 10 6, 7, 8, 9, 10 7, 8, 9, 10 5, 6, 7, 8, 9, 10 5, 6, 7, 8, 9, 10 7, 8, 9 9 6, 7, 8, 9 7, 8, 9 5, 6, 7, 8, 9 6, 7, 8, 9 4, 5, 6, 7, 8, 9 4, 5, 6, 7, 8, 9 Read Latency Write Latency Note Note Write Latency = Read Latency-1 Preliminary Data Sheet M17507EJ2V0DS 15 PD46128512-X Figure 4-1. Latency Definition CLK (Input) Address (Input) Valid /ADV (Input) /CE1 (Input) RL = 5 DQ (Output) Read Latency = 5 High-Z Write Latency = 4 Q0 Q1 Q2 Q3 Q4 Q5 DQ (Input) High-Z D0 D1 D2 D3 D4 D5 D6 RL = 6 DQ (Output) High-Z Read Latency = 6 Q0 Write Latency = 5 Q1 Q2 Q3 Q4 DQ (Input) High-Z D0 D1 D2 D3 D4 D5 RL = 7 DQ (Output) High-Z Read Latency = 7 Q0 Write Latency = 6 Q1 Q2 Q3 DQ (Input) High-Z D0 D1 D2 D3 D4 RL = 8 DQ (Output) High-Z Read Latency = 8 Q0 Write Latency = 7 Q1 Q2 DQ (Input) High-Z D0 D1 D2 D3 RL = 9 DQ (Output) High-Z Read Latency = 9 Q0 Write Latency = 8 Q1 DQ (Input) High-Z D0 D1 D2 RL = 10 DQ (Output) High-Z Read Latency = 10 Q0 Write Latency = 9 DQ (Input) High-Z D0 D1 16 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X 4.4 Single Write Single write operation is a single-word length synchronous write operation. The PD46128512-X is supporting two type of synchronous write operation, "Burst Read & Single Write" and "Burst Read & Burst Write", configurable with SW bit in the mode register. When the device set to the "Burst Read & Single Write" operation mode, the burst length at the synchronous write operation is always fixed to single word length regardless of the burst length (BL) setting in the mode register, however, BL setting is still effective in synchronous read operation (Refer to 5. Mode Register Settings). Refer to Figure 8-8. Timing Chart. 4.5 /WE Control The PD46128512-X is supporting two type of timing control with /WE input signal, "/WE level control" and "/WE single clock control" configurable with WC bit in the mode register at synchronous write operation. In case of /WE level controlling, /WE must be asserted LOW before the 2nd clock input timing (T1). Refer to Figure 8-8. Synchronous Burst Write Cycle Timing Chart (/WE level Control), Figure 8-9. Synchronous Burst Write Cycle Timing Chart (/WE single clock control). Figure 4-2. /WE Control T0 CLK (Input) T1 T2 T3 T4 T5 T6 T7 Synchronous Burst Write Cycle Timing Chart (/WE level Control), Figure 8-9. Synchronous Burst Write Cycle Timing Chart (/WE single clock control), Figure 8-10. Synchronous Single Write Address (Input) Add /ADV (Input) Read Latency = 5 /CE1 (Input) /WE Level Control /WE (Input) tWES DQ0 to DQ15 (Input) High-Z D0 D1 D2 D3 /WAIT (Output) High-Z /WE Single Clock Control /WE (Input) tWES tWEH DQ0 to DQ15 (Input) High-Z D0 D1 D2 D3 /WAIT (Output) High-Z Preliminary Data Sheet M17507EJ2V0DS 17 PD46128512-X 4.6 Burst Read Suspend/Resume A burst read operation can be suspended by bringing /OE signal from LOW to HIGH during the burst read operation. The /OE signal must be required to meet the specified setup / hold time to the clock which the data being suspended. Once the /OE is brought to HIGH, output data turns to be high impedance state after specific time duration. The burst read suspend will be effective after outputting first read data, or after outputting dummy wait cycles in case of dummy wait cycling insertion at continuous burst read mode. The burst suspend mode will be resumed by re-asserting /OE to LOW, and the first output data is from the same address location as of being suspended. Figure 4-3. Burst Read Suspend/Resume CLK (Input) A0 to A22 (Input) /ADV (Input) H /CE1 (Input) L tSOEH tSOES tSOEH tSOES tSOP tOHZ tBACC tBDH Q1 High-Z tBACC tBDH Q2 Q3 /OE (Input) DQ0 to DQ15 (Output) Q0 18 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X 4.7 Burst Write Suspend/Resume A burst write operation can be suspended by bringing /WE signal from LOW to HIGH during the burst write operation. The /WE signal must be required to meet the specified setup / hold time to the clock which the data being suspended. The burst write suspend will be effective after inputting first write data. The burst suspend mode will be resumed by re-asserting /WE to LOW, and the first write data is written to the same address location as of being suspended. Burst write suspend or resume is available only when WC = 1(/WE level control) is set to the mode register (refer to Table 5-2. Mode Register Definition (5th Bus Cycle). Figure 4-4. Burst Write Suspend/Resume T4 CLK (Input) T5 T6 T7 T8 T9 T10 A0 to A22 (Input) /ADV (Input) H /CE1 (Input) L tWEH tWES tWEH tWES tSWHP tWDS tWDH tWDS tWDH High-Z D2 D3 /WE (Input) DQ0 to DQ15 (Output) D0 D1 Preliminary Data Sheet M17507EJ2V0DS 19 PD46128512-X 4.8 Burst Read Termination Burst read termination can be performed by transferring /CE1 LOW to HIGH during the burst read. When continuous burst length is set, burst read is endless unless it is terminated. Be sure to terminate a burst read after outputting the first read access data. In order to guarantee the last data output, the specified minimum value of /CE1 = LOW hold time (tCEH) against clock edge must be satisfied. In order to perform next operation after burst read termination, the specified minimum value of Burst Read Termination recovery time (tTRB) must be satisfied. Figure 4-5. Burst Read Termination CLK (Input) tACS A0 to A22 (Input) tACH Valid tAH tCHV tCSV tCHV /ADV (Input) tCEH tCES /CE1 (Input) tCHZ /OE (Input) tBACC DQ0 to DQ15 (Output) Q1 Q2 tBDH Q3 High-Z tTRB tCEH tCES 20 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X 4.9 Burst Write Termination Burst write termination can be performed by transferring /CE1 LOW to HIGH during the burst write. When continuous burst length is set, burst write is endless unless it is terminated. Be sure to terminate a burst write after latching the first write data. In order to guarantee the last write data is latched, the specified minimum value of /CE1 = LOW hold time against clock edge must be satisfied. In order to perform next operation after burst write termination, the specified minimum value of Burst Write Termination recovery time (tTRB) must be satisfied. Figure 4-6. Burst Write Termination CLK (Input) tACS A0 to A22 (Input) tACH Valid tAH tCHV tCSV tCHV /ADV (Input) tCEH tCES /CE1 (Input) tWRB tCEH tCES tTRB /WE (Input) tWDS tWDH DQ0 to DQ15 (Output) D1 D2 D3 High-Z Preliminary Data Sheet M17507EJ2V0DS 21 PD46128512-X 4.10 /WAIT 4.10.1 Feature of /WAIT Output The /WAIT output signal indicates the internal status, busy (LOW) or ready (HIGH), during the burst read and burst write operation. The /WAIT output state changes depend on the /CE1 and /ADV condition. When /CE1 held entire LOW, the /WAIT output corresponds with /ADV state and turns to LOW by /ADV assertion. The /WAIT output stays high impedance at standby mode (/CE1 = HIGH) and turns to LOW at active mode brought by /CE1 assertion. The /WAIT output will be asserted to LOW after specific time duration triggered by falling edge of /CE1, or falling edge of /ADV when /CE1 held entire LOW. When the /WAIT output LOW, it indicates the output data is not valid at the next clock cycle. The /WAIT output asserts HIGH one clock cycle before the valid data output. The /WAIT output retains the same state as of the clock cycle right before being suspended with /OE brought to HIGH. Figure 4-7. Burst Read /WAIT Output (/CE1 = HIGH LOW) T0 CLK (Input) T1 T2 T3 T4 T5 A0 to A22 (Input) Add /ADV (Input) /CE1 (Input) /WE (Input) H RL = 5 DQ0 to DQ15 (Output) High-Z tCEWA tCLWA Q0 /WAIT (Output) High-Z 22 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 4-8. Burst Read /WAIT Output (/CE1 = LOW, /ADV = HIGH LOW) T0 CLK (Input) T1 T2 T3 T4 T5 A0 to A22 (Input) Add /ADV (Input) tADWA /CE1 (Input) L /WE (Input) H RL = 5 DQ0 to DQ15 (Output) High-Z tCLWA Q0 /WAIT (Output) The /WAIT output will be asserted to LOW after specific time duration from the falling edge of the /CE1, or falling edge of the /ADV when /CE1 held LOW at burst write operation. When the /WAIT output LOW, it indicates the input data can not be accepted at the next clock cycle. The /WAIT output asserts HIGH one clock cycle before the valid data input. The /WAIT output retains the same state as of the clock cycle right before being suspended with /WE brought to HIGH. The /WAIT output always stay high impedance state under asynchronous mode setting. Preliminary Data Sheet M17507EJ2V0DS 23 PD46128512-X Figure 4-9. Burst Write /WAIT Output (/CE1 = HIGH LOW) T0 CLK (Input) T1 T2 T3 T4 T5 A0 to A22 (Input) Add /ADV (Input) /CE1 (Input) tWES /WE (Input) (WC = 1) tWES tWEH /WE (Input) (WC = 0) RL = 5 DQ0 to DQ15 (Output) High-Z tCEWA /WAIT (Output) High-Z tCLWA D0 D1 Figure 4-10. Burst Write /WAIT Output (/CE1 = LOW, /ADV = HIGH LOW) T0 CLK (Input) T1 T2 T3 T4 T5 A0 to A22 (Input) Add /ADV (Input) tADWA /CE1 (Input) tWES /WE (Input) (WC = 1) tWES tWEH /WE (Input) (WC = 0) RL = 5 DQ0 to DQ15 (Output) High-Z tCLWA /WAIT (Output) D0 D1 24 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X 4.10.2 Dummy Wait Cycles at Continuous Burst Operation In continuous burst operation, dummy wait cycles may be needed when a burst sequence crosses the first 16-word boundary. Whether dummy wait cycles is needed or not depends on start address and the number of dummy wait cycles depends on Read Latency (See Table 4-1. Burst Sequence and 4-2. Dummy Wait Cycles and Read Latency). During the dummy cycle period, /WAIT output LOW. Table 4-1. Burst Sequence Start Address xx00 H xx01 H xx02 H xx03 H xx04 H xx05 H xx06 H xx07 H xx08 H xx09 H xx0A H xx0B H xx0C H xx0D H xx0E H xx0F H xx10 H xx11 H ... xxnB H xxnC H xxnD H xxnE H xxnF H ... ... ... ... ... Burst length = 8 Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Burst length = 16 Linear 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7 9-10-11-12-13-14-15-0-1-2-3-4-5-6-7-8 10-11-12-13-14-15-0-1-2-3-4-5-6-7-8-9 11-12-13-14-15-0-1-2-3-4-5-6-7-8-9-10 12-13-14-15-0-1-2-3-4-5-6-7-8-9-10-11 13-14-15-0-1-2-3-4-5-6-7-8-9-10-11-12 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 ... Continuous Linear 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-... 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-... 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-... 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-... 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19-... 5-6-7-8-9-10-11-12-13-14-15-16-17-18-19-20-... 6-7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-... 7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-22-... 8-9-10-11-12-13-14-15-16-17-18-19-20-21-22-23-... 9-10-11-12-13-14-15-16-17-18-19-20-21-22-23-24-... 10-11-12-13-14-15-16-17-18-19-20-21-22-23-24-25-... 11-12-13-14-15-W-16-17-18-19-20-21-22-23-24-25-... 12-13-14-15-W-W-16-17-18-19-20-21-22-23-24-25-... 13-14-15-W-W-W-16-17-18-19-20-21-22-23-24-25-... 14-15-W-W-W-W-16-17-18-19-20-21-22-23-24-25-... 15-W-W-W-W-W-16-17-18-19-20-21-22-23-24-25-... 16-17-18-19-20-21-22-23-24-25-26-... 17-18-19-20-21-22-23-24-25-26-27-... ... -xxnB -xxnC-xxnD-xxnE-xxnF-W-xx(n+1)0-xx(n+1)1-... -xxnC-xxnD-xxnE-xxnF-W-W-xx(n+1)0-xx(n+1)1-... -xxnD-xxnE-xxnF-W-W-W-xx(n+1)0-xx(n+1)1-... -xxnE-xxnF-W-W-W-W-xx(n+1)0-xx(n+1)1-xx(n+1)2-... -xxnF-W-W-W- W-W-xx(n+1)0-xx(n+1)1-xx(n+1)2-... ... Remarks 1. The above table assumes Read Latency is set 5. W shows Dummy Wait Cycles. 2. Address is in HEX. Preliminary Data Sheet M17507EJ2V0DS 25 PD46128512-X Table 4-2. Dummy Wait Cycles and Read Latency Start Address Read Latency =5 (Write Latency = 4) xxx0 H xxx1 H xxx2 H xxx3 H xxx4 H xxx5 H xxx6 H xxx7 H xxx8 H xxx9 H xxxA H xxxB H xxxC H xxxD H xxxE H xxxF H No wait No wait No wait No wait No wait No wait No wait No wait No wait No wait No wait 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle Read Latency =6 (Write Latency = 5) No wait No wait No wait No wait No wait No wait No wait No wait No wait No wait 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... Read Latency =9 (Write Latency = 6) No wait No wait No wait No wait No wait No wait No wait 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle Read Latency = 10 (Write Latency = 7) No wait No wait No wait No wait No wait No wait 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle Read Latency =n (Write Latency = n-1) No wait No wait No wait No wait No wait No wait (n-9) Wait cycles are needed after boundary data output (n = 10). (n-8) Wait cycles are needed after boundary data output. (n =/> 9) (n-7) Wait cycles are needed after boundary data output. (n =/> 8) (n-6) Wait cycles are needed after boundary data output. (n =/> 7) (n-5) Wait cycles are needed after boundary data output. (n =/> 6) (n-4) Wait cycles are needed after boundary data output. (n =/> 5) (n-3) Wait cycles are needed after boundary data output. (n =/> 5) (n-2) Wait cycles are needed after boundary data output. (n =/> 5) (n-1) Wait cycles are needed after boundary data output. (n =/> 5) n Wait cycles are needed after boundary data output. (n =/> 5) Remark Address is in HEX. 26 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X 4.11 Reset Function from Synchronous Burst Mode to Asynchronous Page Mode Even during the burst operation mode, the PD46128512-X has the reset feature of changing synchronous burst mode to asynchronous page mode. This reset is achieved by toggling CE2 signal HIGH LOW HIGH. This reset to asynchronous page mode can be enable / disable with mode register setting. Since the CE2 signal originally controls partial refresh function, the partial refresh operation can also be performed during the reset operation according to the density specified in the mode register. Please refer to the timing diagram and requirement below. Note that the timing requirement differs with the partial refresh density. In case when the reset to asynchronous page mode is disabled in the mode register, only the partial refresh operation can be performed with CE2 signal toggling. Refer to Figure 2-1. Standby Mode State Machine. Figure 4-11. Reset Entry Timing Chart to Asynchronous Page Mode CLK (Input) tCE2S tRST CE2 (Input) tCES tCHML tMHCL /CE1 (Input) Synchronous Burst Operation Reset to Page Standby Mode2 Asynchronous Page Operation Parameter Reset to asynchronous page and standby mode2 entry /CE1 HIGH to CE2 LOW Reset to asynchronous page and standby mode2 to normal operation CE2 HIGH to /CE1 LOW /CE1 = HIGH setup time to CLK CE2 = LOW hold time to CLK Reset time to asynchronous page mode Symbol tCHML MIN. 0 MAX. Unit ns Note tMHCL 30 300 ns 1 2 s ns ns ns tCES tCE2S tRST 5 1 70 Notes 1. 2. In case the density for partial refresh are 32M bits / 16M bits / 8M bits in standby mode2 In case the density for partial refresh is 0M bits in standby mode2 Preliminary Data Sheet M17507EJ2V0DS 27 PD46128512-X 5. Mode Register Settings The PD46128512-X has several modes, Page Read mode, Burst Read mode, Burst write mode, Single Write mode, Asynchronous Write mode, Deep Power Down mode, Partial Refresh mode. Mode Resister setting defines Partial Refresh Density, Burst Length, Latency, Burst Sequence, Write mode (Burst or Single), Valid Clock Edge, Support burst write suspend/resume or not . The several modes can be set using mode register. Since the initial value of the mode register at power application is undefined, be sure to set the mode register after initialization at power application. 5.1 Mode Register Setting Method To set each mode, write any data twice, write specific data twice, read any address in succession after the highest address (7FFFFFH) is read (6 cycles in total). Cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle Operation Read Write Write Write Write Read Address 7FFFFFH 7FFFFFH 7FFFFFH 7FFFFFH 7FFFFFH Don't care Read Data (RDa) RDa RDa Note Note Data or Don't care or Don't care Code 1 Code 2 Read Data (RDb) Note In order to hold the highest address (7FFFFFH) cell data during mode register setting, be sure to set the same data with 1st cycle read data in the 2nd and 3rd cycle (write cycle). Commands are written to the command register. The command register is used to latch the addresses and data required for executing commands, and it does not have an exclusive memory area. For the timing chart and flow chart, refer to Figure 9-1. Mode Register Setting Timing Chart (Asynchronous Timing + CLK fixed LOW/HIGH), Figure 9-2. Mode Register Setting Timing Chart (Asynchronous Timing + toggle CLK), Figure 9-3. Mode Register Setting Timing Char t (Synchronous Timing), Figure 9-4. Mode Register Setting Flow Chart. Table 5-1, Table 5-2 shows the commands and command sequences. 5.2 Cautions for Setting Mode Register Since, for the mode register setting, the internal counter status is judged by toggling /CE1 and /OE, toggle /CE1 at every cycle during entry (one read cycle, four write cycles and one read cycle), and toggle /OE like /CE1 at the first and the 6th read cycles. If incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the mode register is not performed correctly. Cancellation of the mode register setting must be performed before the write in the 3rd bus cycle is determined. Cancellation in the 4th bus cycle or later should not be performed. If performed, data and previous register setting are not guaranteed, so the mode register must be re-setup after the 6th bus cycle is complete. When the highest address (7FFFFFH) is read consecutively two or more times, the mode register setting entries are not performed correctly. Mode setting is available after power application and read or write operation other than the highest address (7FFFFFH) are performed. Once the several modes have been set in the mode register, these settings are retained until they are set again, while applying the power supply. However, the mode register setting will become undefined except page mode (M = 1) if the power is turned off, so set the mode register again after power application. 28 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X For the timing chart and flow chart, refer Figure 9-1. Mode Register Setting Timing Chart (Asynchronous Timing + CLK fixed LOW/HIGH), Figure 9-2. Mode Register Setting Timing Chart (Asynchronous Timing + toggle CLK), Figure 9-3. Mode Register Setting Timing Char t (Synchronous Timing), Figure 9-4. Mode Register Setting Flow Chart. Table 5-1. Mode Register Definition (4th Bus Cycle) Data Code DQ1, DQ0 Symbol PS Function Partial Refresh Density Value 00 01 10 11 DQ4 to DQ2 BL Burst Length 010 011 111 Others DQ5 M Function Mode 0 1 DQ6 VE Valid Clock Edge 0 1 DQ15 to DQ7 - - 111111111 32M bit 16M bit 8M bit 0M bit 8 word 16 word Continuous Reserved Burst Page Falling Edge Rising Edge Reserved (All "1" are necessary) Description Table 5-2. Mode Register Definition (5th Bus Cycle) Data Code DQ2 to DQ0 Symbol RL Read Latency (Write Latency) Function Value 010 011 100 101 110 111 Others DQ3 SW Single Write 0 1 DQ4 WC /WE Control 0 1 DQ6, DQ5 DQ7 RP - - Reset to Page mode 11 0 1 DQ15 to DQ8 - - 11111111 Description 5 (Write Latency = 4) 6 (5) 7 (6) 8 (7) 9 (8) 10 (9) Reserved Burst Read & Burst Write Burst Read & Single Write Single clock control without suspend Level control with suspend Reserved (All "1" are necessary) Reset available to Page mode Reset not available to Page mode Reserved (All "1" are necessary) Preliminary Data Sheet M17507EJ2V0DS 29 PD46128512-X 5.3 Partial Refresh Density The density for performing refresh in power down mode can be set with mode register. Setting DQ1 and DQ0 to 00 at the 4th bus cycle sets a partial refresh density of 32 M-bit hold; setting DQ1 and DQ0 to 01 at the 4th bus cycle sets a partial refresh density of 16 M-bit hold; setting DQ1 and DQ0 to 10 at the 4th bus cycle sets a partial refresh density of 8 M-bit hold; and setting DQ1 and DQ0 to 11 at the 4th bus cycle sets a partial refresh density of 0 (no hold). Since the Partial Refresh mode is not entered unless CE2 = LOW, when partial refresh is not used, it is not necessary to set the mode register. 5.4 Burst Length Sets the burst length in the burst mode. Setting DQ4 to DQ2 to 010 at the 4th bus sets 8word of burst length; setting DQ4 to DQ2 to 011 at the 4th bus cycle sets 16word of burst length; setting DQ4 to DQ2 to 111 at the 4th bus cycle sets continuous of burst length 5.5 Function Mode Select function mode. Setting DQ5 to 0 at the 4th bus sets a function mode of burst and setting DQ5 to 1 at the 4th bus sets a function mode of page. After power application, page mode is set as an initial state. 5.6 Valid Clock Edge Select valid clock edge (Rising edge or Falling edge) in the burst mode. Setting DQ6 to 0 at the 4th bus cycle sets clock falling edge; setting DQ6 to 1 at the 4th bus cycle sets clock rising edge. 5.7 Read Latency (Write Latency) Sets the number of clock cycles (latency) between the address input and the output of the first data in the burst read mode, the address input and the write data input in the burst write mode. Setting DQ2 to DQ0 to 010 at the 5th bus cycle sets read latency of 5; setting DQ2 to DQ0 to 011 at the 5th bus sets read latency of 6; setting DQ2 to DQ0 to 100 at the 5th bus sets read latency of 7; setting DQ2 to DQ0 to 101 at the 5th bus sets read latency of 8; setting DQ2 to DQ0 to 110 at the 5th bus sets read latency of 9; setting DQ2 to DQ0 to 111 at the 5th bus sets read latency of 10. Once specific RL is set through Mode Register Setting sequence, write latency, that is the number of clock cycles between address input and first write data input, is automatically set to RL-1. For the latency count, refer to Figure 4-1. Latency Definition 5.8 Single Write Sets the write mode. Setting DQ3 to 0 at the 5th bus cycle sets burst write mode; setting DQ3 to 1 at the 5th bus cycle sets single write mode. 30 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X 5.9 /WE Control Sets the /WE timing in burst write operation and burst write suspend / resume available or not. Setting DQ4 to 0 at the 5th bus cycle sets /WE single clock control, and burst write suspend / resume are not supported. In single clock control, /WE is available at the 1st clock edge of /ADV = LOW; setting DQ4 to 1 at the 5th bus cycle sets /WE level control, and burst write suspend / resume are supported. In level control, /WE is sure to transfer LOW to HIGH after latching last write data in burst write operation. Refer to Figure 8-8. Suspend Timing Chart. 5.10 Reset to Page Mode Sets the Reset function from synchronous burst mode to asynchronous page mode. Setting DQ7 to 0 at the 5th bus cycle sets reset available from synchronous burst mode to asynchronous page mode. Setting DQ7 to 1 at the 5th bus cycle sets reset unavailable. 5.11 Reserved Bits Reserved bits must be 1 because reserved bits are used for internal test mode entry. Be sure to set DQ15 to DQ7 to 1 at the 4th and DQ15 to DQ8 and DQ6 and DQ5 at the 5th bus cycles. Synchronous Burst Write Cycle Timing Chart (/WE level Control), Figure 8-9. Synchronous Burst Write Cycle Timing Chart (/WE single clock control), Figure 8-11. Synchronous Burst Write Preliminary Data Sheet M17507EJ2V0DS 31 PD46128512-X 5.12 Cautions for Timing Chart of Setting Mode Register Timing charts for setting mode register are following 3 methods. Power On Asynchronous Mode (Default) 32 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X 6. Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Supply voltage for Output Input / Output voltage Operating ambient temperature Storage temperature Symbol VCC VCCQ VT TA Tstg Condition -0.5 -0.5 Rating Note Note Unit V V V C C to +2.5 to +2.5 to 2.5 -0.5 Note -30 to +85 -55 to +125 Note -1.0 V (MIN.) (Pulse width: 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Supply voltage Supply voltage for Output Input HIGH voltage Input LOW voltage Operating ambient temperature Symbol VCC Note1 Note1 Condition MIN. 1.7 1.7 0.8VCC -0.3 Note2 MAX. 2.0 2.0 VCC+0.3 0.2VCC +85 Unit V V V V C VCCQ VIH VIL TA -30 Notes 1. 2. Use same voltage condition (VCC = VCCQ) -0.5 V (MIN.) (Pulse width: 30 ns) Capacitance (TA = 25C, f = 1 MHz) Parameter Input capacitance Input / Output capacitance Symbol CIN CDQ VIN = 0 V VDQ = 0 V Test condition MIN. TYP. MAX. 8 10 Unit pF pF Remarks 1. 2. VIN: Input voltage, VDQ: Input / Output voltage These parameters are not 100% tested. Preliminary Data Sheet M17507EJ2V0DS 33 PD46128512-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol Test condition Density of data hold Input leakage current DQ leakage current ILI ILO VIN = 0 V to VCC VDQ = 0 V to VCCQ, /CE1 = VIH or /WE = VIL or /OE = VIH Operating supply current ICCA2 ICCA1 /CE1 = VIL, IDQ = 0 mA, Asynchronous mode Cycle time = 70 ns Cycle time = 85 ns 60 50 50 mA mA -1.0 -1.0 +1.0 +1.0 MIN. TYP. Note1 MAX. Unit A A /CE1 = VIL, Frequency = 83 MHz, RL = 7, IDQ = 0 mA, burst length = 1, Synchronous mode Operating supply Burst current Standby supply current ICCA3 /CE1 = VIL, Frequency = 83MHz, RL = 7, IDQ = 0 mA, burst length = Continuous 30 mA ISB1 ISB2 /CE1 VCC - 0.2 V, CE2 VCC - 0.2 V /CE1 VCC - 0.2 V, CE2 0.2 V 128M bits 32M bits 16M bits 8M bits 0M bit Note2 80 T.B.D. T.B.D. T.B.D. 15 0.8VCCQ 250 T.B.D. T.B.D. T.B.D. 65 A Note2 Note2 Note2 Output HIGH voltage Output LOW voltage VOH VOL IOH = -0.5 mA IOL = 1 mA V 0.2VCCQ V Notes 1. 2. TYP. means reference value measured at TA = 25C. This value is not a guarantee value. The current measured more than 30 ms after standby mode entry (/CE1 changes from LOW to HIGH). It is specified as 2 mA (MAX.) in case of less than 30 ms after /CE1 transition. Remark VIN: Input voltage, VDQ: Input / Output voltage 34 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [For DQ pins] Input Waveform (Rise and Fall Time 3 ns) Vcc 0.8Vcc Vcc / 2 0.2Vcc GND tT Test Points Vcc / 2 Parameter Transition time tT Symbol Test Condition The transition time from 0.8VCC to 0.2VCC and from 0.2VCC to 0.8VCC MAX. 3 Unit ns Output Waveform VccQ / 2 Test Points VccQ / 2 Output Load 30 pF [For all other input pins] Input Waveform (Rise and Fall Time 3 ns) Vcc 0.8Vcc Vcc / 2 0.2Vcc GND Test Points Vcc / 2 tT Parameter Transition time tT Symbol Test Condition The transition time from 0.8VCC to 0.2VCC and from 0.2VCC to 0.8VCC MAX. 3 Unit ns Preliminary Data Sheet M17507EJ2V0DS 35 PD46128512-X 7. Asynchronous AC Specification, Timing Chart Asynchronous Read Cycle Parameter Read cycle time Address access time /CE1 access time /OE to output valid /LB, /UB to output valid Output hold from address change Page read cycle time Page access time /CE1 to output in low impedance /OE to output in low impedance /LB, /UB to output in low impedance /CE1 to output in high impedance /OE to output in high impedance /LB, /UB to output in high impedance Address set to /CE1 LOW Address invalid time Address set to /OE LOW /OE HIGH to address hold /CE1 HIGH to address hold /CE1 LOW to /OE LOW /OE LOW to /CE1 HIGH Address set to /ADV HIGH /ADV HIGH to address hold /ADV LOW pulse width /CE1 HIGH pulse width /LB, /UB HIGH pulse width /OE HIGH pulse width /OE HIGH to /WE set /WE HIGH to /OE set Symbol tRC tAA tACE tOE tBA tOH tPRC tPAA tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tASC tAX tASO tOHAH tCHAH tCLOL tOLCH tASV tAH tVPL tCP tBP tOP tOES tOEH 0 -5 0 -5 45 7 3 7 10 10 10 10 10 10,000 10,000 10,000 +10,000 -15 15 0 -5 0 -5 60 7 3 7 10 10 10 10 10 10,000 10,000 10,000 +10,000 10 5 5 9 9 9 -15 15 3 20 20 10 5 5 9 9 9 -E9X, -E11X MIN. 70 70 70 45 45 3 25 25 MAX. -E10X, -E12X MIN. 85 85 85 60 60 MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 4 3 2 1 Unit Note Notes 1. 2. 3. 4. Output load: 30 pF Output load: 5 pF tAX (MAX.) is applied while /CE1, /OE and /ADV are being hold at LOW. When tASO | tCHAH |, tCHAH (MIN.) is -15 ns. tCHAH Address (Input) /CE1 (Input) /OE (Input) tASO 5. tOP, tOES and tOEH (MAX.) are applied while /CE1 is being hold at LOW. 36 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Asynchronous Write Cycle Parameter Symbol -E9X, -E11X MIN. Write cycle time /CE1 to end of write Address valid to end of write /LB, /UB to end of write Write pulse width Write recovery time Write recovery time (/WE = HIGH /CE1 = HIGH) /CE1 pulse width /LB, /UB HIGH pulse width /WE HIGH pulse width /WE HIGH pulse width (/CE1 = LOW) Address setup time /CE1 HIGH to address hold /LB, /UB HIGH to address hold /LB, /UB byte mask setup time /LB, /UB byte mask hold time /LB, /UB byte mask over wrap time Data valid to end of write Data hold time Address set to /ADV HIGH /ADV HIGH to address hold /ADV LOW pulse width /OE HIGH to /WE set /WE HIGH to /OE set tWC tCW tAW tBW tWP tWR tWHCH tCP tBP tWHP tWHP1 tAS tCHAH tBHAH tBS tBH tBWO tDW tDH tASV tAH tVPL tOES tOEH 70 50 55 50 50 0 0 10 10 10 10 0 0 0 0 0 30 25 0 7 3 7 10 10 10,000 10,000 10,000 10,000 MAX. -E10X, -E12X MIN. 85 60 60 60 55 0 0 10 10 10 10 0 0 0 0 0 30 25 0 7 3 7 10 10 10,000 10,000 10,000 10,000 MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 1 Unit Note Notes 1. When tAS | tCHAH | and tCP 18 ns, tCHAH (MIN.) is -15 ns. tCHAH Address (Input) /CE1 (Input) /OE (Input) tASO 2. tOES and tOEH (MAX.) are applied while /CE1 is being hold at LOW. Preliminary Data Sheet M17507EJ2V0DS 37 PD46128512-X Figure 7-1. Asynchronous Read Cycle Timing Chart 1 (Basic Timing1) tRC Address (Input) A1 /ADV (Input) L tASC tACE tCHAH /CE1 (Input) tCLZ tCLOL tOE /OE (Input) tOLZ tBA /LB, /UB (Input) tBLZ DQ (Output) High-Z Data Out Q1 tBHZ High-Z tOHZ tCHZ tCP Cautions 1. 2. In read cycle, CE2 and /WE should be fixed HIGH. CLK should be fixed HIGH or LOW. Figure 7-2. Asynchronous Read Cycle Timing Chart 2-1 (Basic Timing2-1) tRC Address (Input) tASV A1 A2 tAH tVPL /ADV (Input) tASC tASC /CE1 (Input) tCP tCLOL /OE (Input) tOLZ tBA /LB, /UB (Input) tBHZ tBLZ tOHZ tOE tCHZ tVPL tACE DQ (Output) High-Z Data Out Q1 High-Z Cautions 1. 2. 38 In read cycle, CE2 and /WE should be fixed HIGH. CLK should be fixed HIGH or LOW. Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 7-3. Asynchronous Read Cycle Timing Chart 2-2 (Basic Timing2-2) tRC Address (Input) tASV A1 A2 tAH tVPL /ADV (Input) tASC tASC /CE1 (Input) tCP tCHZ /OE (Input) tVPL tACE L tBA /LB, /UB (Input) tBHZ tBLZ DQ (Output) High-Z Data Out Q1 High-Z Cautions 1. 2. In read cycle, CE2 and /WE should be fixed HIGH. CLK should be fixed HIGH or LOW. Figure 7-4. Asynchronous Read Cycle Timing Chart 2-3 (Basic Timing2-3) Address (Input) tASV A1 A2 tAH tVPL /ADV (Input) tRC tAA /CE1 (Input) L tASO tOE /OE (Input) tOLZ tBA /LB, /UB (Input) tBHZ tBLZ tOHZ tASO DQ (Output) High-Z Data Out Q1 High-Z Cautions 1. 2. In read cycle, CE2 and /WE should be fixed HIGH. CLK should be fixed HIGH or LOW. Preliminary Data Sheet M17507EJ2V0DS 39 PD46128512-X Figure 7-5. Asynchronous Read Cycle Timing Chart 3 (/CE1 Controlled) tRC tRC Address (Input) tASC tACE A1 tCHAH tASC tACE A2 tCHAH A3 /CE1 (Input) tCP tCLZ /OE (Input) L tCHZ tCLZ tCHZ tCP /LB, /UB (Input) L DQ (Output) High-Z Data Out Q1 High-Z Data Out Q2 High-Z Cautions 1. In read cycle, CE2 and /WE should be fixed HIGH. 2. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. Figure 7-6. Asynchronous Read Cycle Timing Chart 4 (/OE Controlled) tRC tRC Address (Input) A1 A2 A3 tAA /CE1 (Input) tAA L tASO tOE tOHAH tASO tOE tOHAH tASO /OE (Input) tOP /LB, /UB (Input) tOLZ High-Z Data Out Q1 tOHZ High-Z tOLZ tOHZ High-Z tOP DQ (Output) Data Out Q2 Cautions 1. 2. In read cycle, CE2 and /WE should be fixed HIGH. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. 40 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 7-7. Asynchronous Read Cycle Timing Chart 5 (/CE1, /OE Controlled) tRC tRC Address (Input) tACE A1 tOHAH tAA A2 tCHAH tOLCH A3 /CE1 (Input) tCLZ tCLOL /OE (Input) tASO tOHZ tOLZ /LB, /UB (Input) tOLZ tOE tOHZ tASO tOE tCHZ tOHAH DQ (Output) High-Z Data Out Q1 High-Z Data Out Q2 High-Z Cautions 1. 2. In read cycle, CE2 and /WE should be fixed HIGH. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. Figure 7-8. Asynchronous Read Cycle Timing Chart 6 (Address Controlled) tRC tRC Address (Input) tAX tAA A1 tAX tAA A2 A3 /CE1 (Input) L /OE (Input) L /LB, /UB (Input) L tOH tOH tOH DQ (Output) Data Out Q1 Data Out Q2 Cautions 1. 2. In read cycle, CE2 and /WE should be fixed HIGH. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. Preliminary Data Sheet M17507EJ2V0DS 41 PD46128512-X Figure 7-9. Asynchronous Read Cycle Timing Chart 7 (/LB, /UB Controlled) tRC tRC Address (Input) tAX tAA A1 tAX tAA A2 A3 /CE1 (Input) L /OE (Input) L /LB, /UB (Input) tBA tBLZ DQ (Output) High-Z tBHZ Data Out Q1 tBP tBA tBLZ High-Z tBHZ Data Out Q2 tBP High-Z Cautions 1. 2. In read cycle, CE2 and /WE should be fixed HIGH. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. Figure 7-10. Asynchronous Page Read Cycle Timing Chart tRC tPRC tPRC tPRC tPRC tPRC tPRC tPRC Address (A4-A22) (Input) Page Address (A0-A3) (Input) AN AN+1 AN+2 AN+3 AN+4 AN+5 AN+6 AN+7 tOH /CE1 (Input) tCHZ tASO tOE /OE (Input) tAA tOHZ tPAA tOH High-Z QN QN+1 QN+2 QN+3 QN+4 QN+5 QN+6 QN+7 tPAA tOH tPAA tOH tPAA tOH tPAA tOH tPAA tOH tPAA tOH DQ (Output) Cautions 1. 2. 3. 4. 5. In read cycle, CE2 and /WE should be fixed HIGH. /LB and /UB should be fixed LOW. /ADV should be fixed LOW. CLK should be fixed HIGH or LOW. Fix /CE1 and /OE to LOW throughout a page operation. Arbitrary order and combination of A0-A3 is possible in the page operation. 42 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 7-11. Asynchronous Write Cycle Timing Chart 1 (Basic Timing1) tWC Address (Input) A1 /ADV (Input) L tAS tCW tWR /CE1 (Input) tAS tWP tWR /WE (Input) tAS /LB, /UB (Input) tOES /OE (Input) tDW DQ (Input) High-Z Data In D1 tDH High-Z tBW tWR Cautions 1. 2. 3. 4. During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should be inactivated. Do not input data to the DQ pins while they are in the output state. In write cycle, CE2 and /OE should be fixed HIGH. CLK should be fixed HIGH or LOW. Remark Write operation is done during the overlap time of LOW of following signals. * /CE1 * /WE * /LB and/or /UB Preliminary Data Sheet M17507EJ2V0DS 43 PD46128512-X Figure 7-12. Asynchronous Write Cycle Timing Chart 2 (Basic Timing2) tWC tWC Address (Input) tASV tVPL /ADV (Input) tVPL tASC tCW tWR tAS A1 tAH A2 /CE1 (Input) tAS /WE (Input) tAS /LB, /UB (Input) tOES /OE (Input) tDW DQ (Input) High-Z tDH High-Z tBW tWR tAS tWP tWR tAS Data In D1 Cautions 1. 2. 3. 4. During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should be inactivated. Do not input data to the DQ pins while they are in the output state. In write cycle, CE2 and /OE should be fixed HIGH. CLK should be fixed HIGH or LOW. Remark Write operation is done during the overlap time of LOW of following signals. * /CE1 * /WE * /LB and/or /UB 44 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 7-13. Asynchronous Write Cycle Timing Chart 3 (/CE1 Controlled) tWC tWC Address (Input) tAS A1 tCW tWR tAS A2 tCW tWR A3 /CE1 (Input) tCP tCP /WE (Input) L /LB, /UB (Input) L tOHAH tOES tOEH tASO /OE (Input) tDW DQ (Input) High-Z tDH High-Z tDW tDH High-Z Data In D1 Data In D2 Cautions 1. 2. 3. 4. During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should be inactivated. Do not input data to the DQ pins while they are in the output state. In write cycle, CE2 and /OE should be fixed HIGH. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. Remark Write operation is done during the overlap time of LOW of following signals. * /CE1 * /WE * /LB and/or /UB Preliminary Data Sheet M17507EJ2V0DS 45 PD46128512-X Figure 7-14. Asynchronous Write Cycle Timing Chart 4 (/WE Controlled) tWC tWC Address (Input) A1 tCHAH A2 tCHAH A3 tCW /CE1 (Input) tAS tWP tCW tWHCH tCP tAS tWP tWHCH tCP /WE (Input) tWHP /LB, /UB (Input) tOHAH tOES /OE (Input) tDW DQ (Input) High-Z tDH High-Z tDW tDH High-Z tOEH tASO Data In D1 Data In D2 Cautions 1. 2. 3. 4. During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should be inactivated. Do not input data to the DQ pins while they are in the output state. In write cycle, CE2 and /OE should be fixed HIGH. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. Remark Write operation is done during the overlap time of LOW of following signals. * /CE1 * /WE * /LB and/or /UB 46 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 7-15. Asynchronous Write Cycle Timing Chart 5 (/WE Controlled) tWC tWC Address (Input) A1 A2 A3 tAW /CE1 (Input) tAW L tAS tWP tWR tAS tWP tWR /WE (Input) tWHP1 /LB, /UB (Input) tOHAH tOES /OE (Input) tDW DQ (Input) High-Z tDH Data In D1 High-Z tDW tDH Data In D2 High-Z tOEH tASO Cautions 1. 2. 3. 4. During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should be inactivated. Do not input data to the DQ pins while they are in the output state. In write cycle, CE2 and /OE should be fixed HIGH. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. Remark Write operation is done during the overlap time of LOW of following signals. * /CE1 * /WE * /LB and/or /UB Preliminary Data Sheet M17507EJ2V0DS 47 PD46128512-X Figure 7-16. Asynchronous Write Cycle Timing Chart 6 (/LB, /UB Controlled) tWC tWC Address (Input) A1 A2 A3 /CE1 (Input) L /WE (Input) tAS tBW tWR tAS tBW tWR /LB, /UB (Input) tOHAH tOES /OE (Input) tDW DQ (Input) High-Z tDH tBP tBP tASO tOEH tDW High-Z tDH High-Z Data In D1 Data In D2 Cautions 1. 2. 3. 4. During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should be inactivated. Do not input data to the DQ pins while they are in the output state. In write cycle, CE2 and /OE should be fixed HIGH. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. Remark Write operation is done during the overlap time of LOW of following signals. * /CE1 * /WE * /LB and/or /UB 48 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 7-17. Asynchronous Write Cycle Timing Chart 7 (/LB, /UB Independent Controlled 1) tWC tWC Address (Input) A1 A2 A3 /CE1 (Input) L /WE (Input) tAS tBW tWR /LB (Input) tAS tBW tWR /UB (Input) tOHAH tOES /OE (Input) tBP tASO tOEH tDW DQ0 to DQ7 (Input) High-Z tDH Data In D1 High-Z tDW DQ8 to DQ15 (Input) High-Z tDH High-Z Data In D2 Cautions 1. 2. 3. 4. During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should be inactivated. Do not input data to the DQ pins while they are in the output state. In write cycle, CE2 and /OE should be fixed HIGH. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. Remark Write operation is done during the overlap time of LOW of following signals. * /CE1 * /WE * /LB and/or /UB Preliminary Data Sheet M17507EJ2V0DS 49 PD46128512-X Figure 7-18. Asynchronous Write Cycle Timing Chart 8 (/LB, /UB Independent Controlled 2) tWC tWC Address (Input) A1 A2 A3 /CE1 (Input) L tAS tBW tWR /WE (Input) tWP tWR tBH /LB (Input) tBS tAS /UB (Input) tBP tOHAH tOES /OE (Input) tOEH tASO tDW DQ0 to DQ7 (Input) High-Z tDH High-Z Data In D1 tDW DQ8 to DQ15 (Input) High-Z tDH High-Z Data In D2 Cautions 1. 2. 3. 4. During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should be inactivated. Do not input data to the DQ pins while they are in the output state. In write cycle, CE2 and /OE should be fixed HIGH. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. Remark Write operation is done during the overlap time of LOW of following signals. * /CE1 * /WE * /LB and/or /UB 50 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 7-19. Asynchronous Write Cycle Timing Chart 9 (/LB, /UB Independent Controlled 3) tWC tWC Address (Input) A1 A2 A3 /CE1 (Input) L tAS tWP tWR tAS tWP tWR /WE (Input) tWHP1 tBS /LB (Input) tBS tBH tBH /UB (Input) tOHAH tOES /OE (Input) tOEH tASO tDW DQ0 to DQ7 (Input) High-Z tDH High-Z Data In D1 tDW DQ8 to DQ15 (Input) High-Z tDH High-Z Data In D2 Cautions 1. 2. 3. 4. During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should be inactivated. Do not input data to the DQ pins while they are in the output state. In write cycle, CE2 and /OE should be fixed HIGH. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. Remark Write operation is done during the overlap time of LOW of following signals. * /CE1 * /WE * /LB and/or /UB Preliminary Data Sheet M17507EJ2V0DS 51 PD46128512-X Figure 7-20. Asynchronous Write Cycle Timing Chart 10 (/LB, /UB Independent Controlled 4) tWC tWC Address (Input) A1 A2 A3 /CE1 (Input) L tAS tBW tWR tAS tBW tWR /WE (Input) tWHP1 tBS /LB (Input) tBS tBH tBH /UB (Input) tOHAH tOES /OE (Input) tOEH tASO tDW DQ0 to DQ7 (Input) High-Z tDH High-Z Data In D1 tDW DQ8 to DQ15 (Input) High-Z tDH High-Z Data In D2 Cautions 1. 2. 3. 4. During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should be inactivated. Do not input data to the DQ pins while they are in the output state. In write cycle, CE2 and /OE should be fixed HIGH. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. Remark Write operation is done during the overlap time of LOW of following signals. * /CE1 * /WE * /LB and/or /UB 52 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 7-21. Asynchronous Write Cycle Timing Chart 11 (/LB, /UB Independent Controlled 5) tWC tWC Address (Input) A1 A2 A3 /CE1 (Input) L tAS tBW tWR tAS tBW tWR /WE (Input) tWHP1 tBS /LB (Input) tBS tBH tBH /UB (Input) tOHAH tOES /OE (Input) tOEH tASO tDW DQ0 to DQ7 (Input) High-Z tDH High-Z Data In D1 tDW DQ8 to DQ15 (Input) High-Z tDH High-Z Data In D2 Cautions 1. 2. 3. 4. During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should be inactivated. Do not input data to the DQ pins while they are in the output state. In write cycle, CE2 and /OE should be fixed HIGH. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. Remark Write operation is done during the overlap time of LOW of following signals. * /CE1 * /WE * /LB and/or /UB Preliminary Data Sheet M17507EJ2V0DS 53 PD46128512-X Figure 7-22. Asynchronous Write Cycle Timing Chart 12 (/LB, /UB Independent Controlled 6) tWC tWC Address (Input) A1 A2 A3 /CE1 (Input) L /WE (Input) tAS tBW tWR tAS tBW tWR /LB (Input) tAS tBW tBWO /UB (Input) tOHAH tOES /OE (Input) tOEH tASO tWR tAS tBW tBWO tWR tDW DQ0 to DQ7 (Input) High-Z tDH Data In D1 tDW tDH Data In D2 High-Z tDW DQ8 to DQ15 (Input) High-Z tDH Data In D1 tDW tDH High-Z Data In D2 Cautions 1. 2. 3. 4. During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should be inactivated. Do not input data to the DQ pins while they are in the output state. In write cycle, CE2 and /OE should be fixed HIGH. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. Remark Write operation is done during the overlap time of LOW of following signals. * /CE1 * /WE * /LB and/or /UB 54 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 7-23. Asynchronous Write-Read Cycle Timing Chart tWC tRC Address (Input) A1 tAS /CE1 (Input) tAS /WE (Input) tCW tAA tRC tCHZ tWP tOEH /OE (Input) tOLZ tAS /LB, /UB (Input) tBW tOE tOHZ tBHZ tDW DQ (Input/Output) High-Z tDH High-Z Data Out Q1 High-Z Data In D1 Cautions 1. 2. 3. 4. During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should be inactivated. Do not input data to the DQ pins while they are in the output state. In write cycle, CE2 and /OE should be fixed HIGH. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. Remark Write operation is done during the overlap time of LOW of following signals. * /CE1 * /WE * /LB and/or /UB Preliminary Data Sheet M17507EJ2V0DS 55 PD46128512-X Figure 7-24. Asynchronous Read-Write Cycle Timing Chart tRC tRC tWC Address (Input) tAA tACE /CE1 (Input) tCLZ A1 tWR tCW tWP tWR /WE (Input) tASO /OE (Input) tOLZ tBA /LB, /UB (Input) tBLZ tDW DQ (Input/Output) High-Z Data Out Q1 High-Z tDH High-Z tOHZ tWR tBW tOE tOES Data In D1 Cautions 1. 2. 3. 4. During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should be inactivated. Do not input data to the DQ pins while they are in the output state. In write cycle, CE2 and /OE should be fixed HIGH. /ADV should be fixed LOW or toggled HIGH LOW HIGH. CLK should be fixed HIGH or LOW. Remark Write operation is done during the overlap time of LOW of following signals. * /CE1 * /WE * /LB and/or /UB 56 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X 8. Synchronous AC Specification, Timing Chart Synchronous Read / Write Common Specification Parameter Symbol -E9X, -E10X MIN. Clock Specifications Cycle frequency CLK HIGH width CLK LOW width CLK rise / fall time Address Latching Specifications Address setup time to CLK Address hold time to CLK /ADV setup time to CLK /ADV hold time from CLK /ADV = LOW pulse width Address hold time from /ADV = HIGH /CE1 setup time to CLK Asynchronous Specification /CE1 to output in low impedance /OE to output in low impedance /LB, /UB to output in low impedance /CE1 to output in high impedance /OE to output in high impedance /LB, /UB to output in high impedance /WAIT Specification /WAIT output time from /CE1 = LOW /WAIT output time from /ADV = LOW /WAIT = HIGH output time from CLK /WAIT in high impedance from /CE1 = HIGH Others /CE1 hold time /LB, /UB hold time /CE1 HIGH pulse width tCEH tLUH tCP 1 1 10 1 1 10 ns ns ns tCEWA tADWA tCLWA tCWHZ 10 10 7 10 13 13 8 10 ns ns ns ns 2 3 tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ 10 5 5 9 9 9 10 5 5 9 9 9 ns ns ns ns ns ns 2 tACS tACH tCSV tCHV tVPL tAH tCES 5 4 5 1 7 3 5 10,000 5 4 5 1 7 3 5 10,000 ns ns ns ns ns ns ns tCYCLE tCH tCL tCHCL 0.1 3 3 3 108 0.1 3 3 3 83 MHz ns ns ns 1 MAX. -E11X, -E12X MIN. MAX. Unit Note Notes 1. 2. 3. Case BL (Burst Length) = Continuous : 2 MHz (MIN.) Output load: 5 pF Output load: 30 pF Preliminary Data Sheet M17507EJ2V0DS 57 PD46128512-X Synchronous Burst Read Cycle Parameter Symbol -E9X, -E10X MIN. Synchronous Read Specifications Burst access time Output data hold time /OE setup time to CLK for data output /LB, /UB setup time to CLK for data output /OE setup time for burst read suspend /OE hold time for burst read suspend Burst read suspend time (/OE = HIGH) Burst read termination recovery time tBACC tBDH tOC tBC tSOES tSOEH tSOP tTRB 2 30 30 5 1 9 18 10,000 7 2 30 30 5 1 12 24 10,000 8 ns ns ns ns ns ns ns ns 1 MAX. -E11X, -E12X MIN. MAX. Unit Note Note1. Output load: 30 pF Synchronous Burst Write Cycle Parameter Symbol -E9X, -E10X MIN. Synchronous Write Specifications /LB, /UB setup time to CLK for latching data /WE setup time for CLK (In /WE single clock control operation) (In burst write suspend operation) /WE hold time in the write operation (In /WE single clock control operation) (In burst write suspend operation) Write data setup time Write data hold time /WE HIGH pulse width /ADV LOW from CLK for latching the latest data Burst write termination recovery time tWDS tWDH tSWHP tWRB tTRB 5 1 9 2 18 10,000 5 1 12 2 24 10,000 ns ns ns CLK ns tWEH 1 1 ns tWES 5 5 ns tBC 30 30 ns MAX. -E11X, -E12X MIN. MAX. Unit Note 58 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 8-1. Synchronous CLK Input Timing Chart tCL CLK (Input) tCYCLE tCH tCHCL VIH VIL Figure 8-2. Synchronous Burst Read Cycle Timing Chart (/CE1 Control) T0 T1 T2 tCYCLE CLK (Input) tACS Address (Input) tACH Valid tAH tCHV tCSV tCHV /ADV (Input) tVPL tCES tCLZ tCEWA /CE1 (Input) tCP /OE (Input) tCWHZ L tCEWA tCEH tVPL tCES tCLZ tCHV tCSV tCHV tCH tCL tCHCL tCHCL tACS tACH T3 T4 T5 T6 Tm Tn T0 T1 T2 T3 T4 Valid tAH /WE (Input) H /LB, /UB (Input) L tCLWA /WAIT (Output) High-Z tCHZ RL = 5 tBACC tBDH Q0 Q1 tBDH QBL High-Z High-Z DQ (Output) High-Z Remarks 1. 2. 3. The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16. QBL means the latest data out of burst length. CE2 should be fixed HIGH. Valid clock edge is the rising edge. Preliminary Data Sheet M17507EJ2V0DS 59 PD46128512-X Figure 8-3. Synchronous Burst Read Cycle Timing Chart (/ADV Control) T0 T1 T2 tCYCLE CLK (Input) tACS Address (Input) tACH Valid tAH tCHV tCSV tCHV /ADV (Input) tVPL tADWA /CE1 (Input) L tVPL tADWA tCHV tCSV tCHV tCH tCL tCHCL tCHCL tACS tACH T3 T4 T5 T6 Tm Tn T0 T1 T2 T3 T4 Valid tAH /OE (Input) L /WE (Input) H /LB, /UB (Input) L tCLWA tCLWA /WAIT (Output) RL = 5 tBACC DQ (Output) tBDH Q0 Q1 tBDH QBL Remarks 1. 2. 3. The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16. QBL means the latest data out of burst length. CE2 should be fixed HIGH. Valid clock edge is the rising edge. 60 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 8-4. Synchronous Burst Read Cycle Timing Chart (/OE Control) T0 T1 T2 tCYCLE CLK (Input) tACS Address (Input) tACH Valid tAH tCHV tCSV tCHV /ADV (Input) tVPL tVPL tCHV tCSV tCHV tCH tCL tCHCL tCHCL tACS tACH Valid tAH T3 T4 T5 T6 Tm Tn T0 T1 T2 T3 T4 tADWA /CE1 (Input) L tOC /OE (Input) tOLZ /WE (Input) H tBC /LB, /UB (Input) tBLZ /WAIT (Output) RL = 5 tBACC DQ (Output) High-Z tBDH Q0 Q1 tBDH QBL tCLWA tBHZ tOHZ tSOEH tADWA tOLZ tBLZ tCLWA High-Z Remarks 1. 2. 3. 4. The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16. QBL means the latest data out of burst length. CE2 should be fixed HIGH. Valid clock edge is the rising edge. tOC and tBC are defined from CLK rising edge of RL-1 to /OE = LOW, /LB and /UB = LOW. Preliminary Data Sheet M17507EJ2V0DS 61 PD46128512-X Figure 8-5. Synchronous Burst /WAIT Timing Chart (Continuous) T0 T1 T2 tCYCLE CLK (Input) tACS Address (Input) tACH tCH tCL tCHCL tCHCL T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 ADDmf tAH tCHV tCSV tCHV /ADV (Input) tVPL tCES /CE1 (Input) tCEWA tCLZ tOC /OE (Input) tOLZ /WE (Input) H tBC /LB, /UB (Input) tBLZ /WAIT (Output) High-Z tCLWA tCLWA tCLWA RL = 5 tBACC DQ (Output) High-Z tBDH Qmf Qn0 Qn1 Remarks 1. 2. 3. 4. 5. The above timing chart assumes Burst length is continuous. CE2 should be fixed HIGH. Valid clock edge is the rising edge. tOC and tBC are defined from CLK rising edge of RL-1 to /OE = LOW, /LB and /UB = LOW. The above timing chart assumes Read Latency is 5 and start address is from xxxfH and the number of dummy wait cycles are 5 cycles. 62 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 8-6. Synchronous Burst Read Suspend Timing Chart T0 T1 T2 tCYCLE CLK (Input) tACS Address (Input) tACH Valid tAH tCHV tCSV tCHV /ADV (Input) tVPL tCES tCLZ tCEWA /CE1 (Input) tOC tOLZ /OE (Input) tSOP /WE (Input) H tBC tBLZ /LB, /UB (Input) tCLWA /WAIT (Output) High-Z tSOEH tSOES tSOEH tSOES tCH tCL tCHCL tCHCL T3 T4 T5 T6 T7 T8 T9 T10 RL = 5 tBACC DQ (Output) High-Z tBDH Q0 High-Z tBACC tBDH Q1 Q2 Q3 Q4 Remarks 1. 2. 3. 4. 5. The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16. CE2 should be fixed HIGH. Valid clock edge is the rising edge. tOC and tBC are defined from CLK rising edge of RL-1 to /OE = LOW, /LB and /UB = LOW. Burst read suspend is valid after outputting the first read access data (Q0). Preliminary Data Sheet M17507EJ2V0DS 63 PD46128512-X Figure 8-7. Synchronous Burst Read Termination Cycle Timing Chart T0 T1 T2 tCYCLE CLK (Input) tACS Address (Input) tACH Valid tAH tCHV tCSV tCHV /ADV (Input) tVPL tCES tCLZ tCEWA /CE1 (Input) tTRB tOC tOLZ /OE (Input) tCEH tCES tVPL tCES tCLZ tCEWA tCHV tCSV tCHV tCH tCL tCHCL tCHCL tACS tACH T3 T4 T0 T1 T2 T3 T4 Valid tAH /WE (Input) H tBC tBLZ /LB, /UB (Input) tCLWA High-Z /WAIT (Output) RL = 5 tBACC High-Z DQ (Output) tBDH Q0 High-Z tCHZ tCWHZ High-Z Remarks 1. 2. 3. 4. 5. 6. 7. The above timing chart assumes Read Latency is 5. CE2 should be fixed HIGH. Valid clock edge is the rising edge. tOC and tBC are defined from CLK rising edge of RL-1 to /OE = LOW, /LB and /UB = LOW. tTRB is specified from /CE1 de-assert to /CE1 assert for next operation. Burst read termination is valid after outputting the first read access data (Q0). In case continuous burst read is set, /CE1 de-assert is needed for burst read termination. 64 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 8-8. Synchronous Burst Write Cycle Timing Chart (/WE Level Control) T0 T1 T2 tCYCLE CLK (Input) tACS Address (Input) tACH Valid tAH tCHV tCSV tCHV /ADV (Input) tVPL tWRB tCES tCEWA /CE1 (Input) tCEH tCWHZ tCEH tCES tCEWA tVPL tCHV tCSV tCHV tCH tCL tACS tACH Valid tAH T3 T4 T5 Tl Tm Tn T0 T1 /OE (Input) H tWES tWEH /WE (Input) tBC /LB, /UB (Input) tCLWA /WAIT (Output) High-Z High-Z tLUH RL = 5 tWDS tWDH DQ (Input) High-Z D0 D1 DBL High-Z Remarks 1. 2. 3. 4. The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16. DBL means the latest data input of burst length. CE2 should be fixed HIGH. Valid clock edge is the rising edge. tBC is defined from CLK rising edge of RL-1 to /LB and /UB = LOW. Preliminary Data Sheet M17507EJ2V0DS 65 PD46128512-X Figure 8-9. Synchronous Burst Write Cycle Timing Chart (/WE Single Clock Control) T0 T1 T2 tCYCLE CLK (Input) tACS Address (Input) tACH Valid tAH tCHV tCSV tCHV /ADV (Input) tVPL tWRB tCES tCEWA /CE1 (Input) tCEH tCWHZ tCEH tCES tCEWA tVPL tCHV tCSV tCHV tCH tCL tACS tACH Valid tAH T3 T4 T5 Tl Tm Tn T0 T1 /OE (Input) H tWES tWEH tWES tWEH /WE (Input) tBC /LB, /UB (Input) tCLWA /WAIT (Output) High-Z High-Z tLUH RL = 5 tWDS tWDH DQ (Input) High-Z D0 D1 DBL High-Z Remarks 1. 2. 3. 4. The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16. DBL means the latest data input of burst length. CE2 should be fixed HIGH. Valid clock edge is the rising edge. tBC is defined from CLK rising edge of RL-1 to /LB and /UB = LOW. 66 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 8-10. Synchronous Single Write Cycle Timing Chart (/WE level Control) T0 T1 T2 tCYCLE CLK (Input) tACS Address (Input) tACH Valid tAH tCHV tCSV tCHV /ADV (Input) tVPL tWRB tCES /CE1 (Input) tCEWA tCEWA tCEH tVPL tADWA tCES tCHV tCSV tCHV tCH tCL tACS tACH T3 T4 T0 T1 T2 T3 Valid tAH /OE (Input) H tWES tWEH /WE (Input) tBC /LB, /UB (Input) tCLWA High-Z /WAIT (Output) RL = 5 tLUH tWDS tWDH High-Z DQ (Input) D0 High-Z Remarks 1. 2. 3. 4. The above timing chart assumes Read Latency is 5. CE2 should be fixed HIGH. Valid clock edge is the rising edge. tBC is defined from CLK rising edge of RL-1 to /LB and /UB = LOW. Preliminary Data Sheet M17507EJ2V0DS 67 PD46128512-X Figure 8-11. Synchronous Burst Write Suspend Timing Chart T0 T1 T2 tCYCLE CLK (Input) tACS Address (Input) tACH tCH tCL tCHCL tCHCL T3 T4 T5 T6 T7 T8 T9 Valid tAH tCHV tCSV tCHV /ADV (Input) tVPL tCES tCEWA /CE1 (Input) /OE (Input) H tWES tWEH tWES tSWHP tBC tWEH tWES /WE (Input) /LB, /UB (Input) tCLWA /WAIT (Output) High-Z RL = 5 tWDS tWDH DQ (Input) High-Z D0 High-Z tWDS tWDH D1 D2 D3 D4 Remarks 1. 2. 3. 4. 5. The above timing chart assumes Read Latency is 5. CE2 should be fixed HIGH. Valid clock edge is the rising edge. tBC is defined from CLK rising edge of RL-1 to /LB and /UB = LOW. Burst write suspend is valid after latching the first write data 68 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 8-12. Synchronous Burst Write Termination Timing Chart T0 T1 T2 tCYCLE CLK (Input) tCH tACS Address (Input) tACH Valid tAH tCHV tCSV tCHV /ADV (Input) tVPL tCES tCEWA /CE1 (Input) tTRB tCEH tCES tWRB tVPL tCES tCEWA tCHV tCSV tCHV tCL tCHCL tCHCL tACS tACH T3 T4 T0 T1 T2 T3 T4 Valid tAH /OE (Input) H tWES /WE (Input) tBC /LB, /UB (Input) tCLWA High-Z /WAIT (Output) RL = 5 tWDS tWDH High-Z DQ (Input/Output) D0 High-Z tWDS tWDH D0 High-Z tCWHZ High-Z tCLWA Remarks 1. 2. 3. 4. 5. 6. The above timing chart assumes Read Latency is 5. CE2 should be fixed HIGH. Valid clock edge is the rising edge. tBC is defined from CLK rising edge of RL-1 to /LB and /UB = LOW. Burst write suspend is valid after latching the first write data In case continuous burst write is set, /CE1 de-assert is needed for burst write termination. Preliminary Data Sheet M17507EJ2V0DS 69 PD46128512-X Figure 8-13. Synchronous Burst Read - Burst Write Cycle Timing Chart (/CE1 Control) tCYCLE CLK (Input) tCH tACS Address (Input) tACH Valid tAH tCHV tCSV tCHV /ADV (Input) tVPL tCES tCEWA tCL tCEH /CE1 (Input) tCP tCHZ tCWHZ tSOEH /OE (Input) tOHZ /WE (Input) tLUH /LB, /UB (Input) tBHZ /WAIT (Output) tCEH tCWHZ tWES tWEH tBC tLUH tCLWA High-Z High-Z RL = 5 tBACC DQ (Input/Output) tBDH QBL High-Z tWDS tWDH D0 DBL High-Z Remarks 1. 2. 3. 4. The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16. QBL means the latest data out of burst length. DBL means the latest data input of burst length. CE2 should be fixed HIGH. Valid clock edge is the rising edge. tBC is defined from CLK rising edge of RL-1 to /LB and /UB = LOW. 70 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 8-14. Synchronous Burst Read - Burst Write Cycle Timing Chart (/ADV Control) tCYCLE CLK (Input) tCH tACS Address (Input) tACH Valid tAH tCHV tCSV tCHV /ADV (Input) tVPL tCL /CE1 (Input) L tSOEH /OE (Input) tOHZ /WE (Input) tLUH /LB, /UB (Input) tBHZ /WAIT (Output) RL = 5 tBACC DQ (Input/Output) tBDH QBL High-Z tWDS tWDH D0 DBL High-Z tADWA tCLWA High-Z tBC tLUH tWES tWEH Remarks 1. 2. 3. 4. The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16. QBL means the latest data out of burst length. DBL means the latest data input of burst length. CE2 should be fixed HIGH. Valid clock edge is the rising edge. tBC is defined from CLK rising edge of RL-1 to /LB and /UB = LOW. Preliminary Data Sheet M17507EJ2V0DS 71 PD46128512-X Figure 8-15. Synchronous Burst Write - Burst Read Cycle Timing Chart (/CE1 Control) tCYCLE CLK (Input) tCH tCL tACS Address (Input) tACH Valid tAH tCHV tCSV tCHV /ADV (Input) tWRB tVPL tCES tCLZ tCEH /CE1 (Input) tCP tCEWA tCWHZ tOC /OE (Input) tOLZ tWEH /WE (Input) tLUH /LB, /UB (Input) tBLZ /WAIT (Output) High-Z tCLWA tBC RL = 5 tWDS tWDH DQ (Input/Output) DBL High-Z tBACC tBDH Q0 Remarks 1. 2. 3. 4. The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16. DBL means the latest data input of burst length. CE2 should be fixed HIGH. Valid clock edge is the rising edge. tOC and tBC are defined from CLK rising edge of RL-1 to /OE = LOW, /LB and /UB = LOW. 72 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 8-16. Synchronous Burst Write - Burst Read Cycle Timing Chart (/ADV Control) tCYCLE CLK (Input) tCH tCL tACS Address (Input) tACH Valid tAH tCHV tCSV tCHV /ADV (Input) tWRB tVPL /CE1 (Input) L tOC /OE (Input) tOLZ tWEH /WE (Input) tLUH /LB, /UB (Input) tBLZ tADWA /WAIT (Output) RL = 5 tWDS tWDH DQ (Input/Output) DBL High-Z tBACC tBDH Q0 tCLWA tBC Remarks 1. 2. 3. 4. The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16. DBL means the latest data input of burst length. CE2 should be fixed HIGH. Valid clock edge is the rising edge. tOC and tBC are defined from CLK rising edge of RL-1 to /OE = LOW, /LB and /UB = LOW. Preliminary Data Sheet M17507EJ2V0DS 73 PD46128512-X 9. Mode Register Setting Timing Figure 9-1. Mode Register Setting Timing Chart (Asynchronous Timing + CLK fixed LOW/HIGH) H CLK (Input) L tRC Address (Input) 7FFFFFH tWC 7FFFFFH tWC 7FFFFFH tWC 7FFFFFH tWC 7FFFFFH tRC Don't care /CE1 (Input) tCE tCHZ tCE tCHZ /OE (Input) tOE /WE (Input) tDW DQ (Input/Output) High-Z RDa High-Z Don't care tDH High-Z Don't care tDW tDH High-Z Code1 tDW tDH High-Z Code2 tDW tDH High-Z RDb High-Z tOHZ tWP tWR tWP tWR tWP tWR tWP tWR tOE tOHZ /LB, /UB (Input) Remarks 1. 2. 3. For the data of Code1 and Code2, refer to Table 5-1. Mode Register Definition (4th Bus Cycle) and Table 5-2. Mode Register Definition (5th Bus Cycle). RDa and RDb are the output data. /ADV fixed LOW or toggle HIGH LOW HIGH. Figure 9-2. Mode Register Setting Timing Chart (Asynchronous Timing + Toggle CLK) CLK (Input) tRC Address (Input) 7FFFFFH tWC 7FFFFFH tWC 7FFFFFH tWC 7FFFFFH tWC 7FFFFFH tRC Don't care /CE1 (Input) tCE tCHZ tCE tCHZ /OE (Input) tOE /WE (Input) tDW DQ (Input/Output) High-Z RDa High-Z Don't care tDH High-Z Don't care tDW tDH High-Z Code1 tDW tDH High-Z Code2 tDW tDH High-Z RDb High-Z tOHZ tWP tWR tWP tWR tWP tWR tWP tWR tOE tOHZ /LB, /UB (Input) Remarks 1. 2. 3. For the data of Code1 and Code2, refer to Table 5-1. Mode Register Definition (4th Bus Cycle) and Table 5-2. Mode Register Definition (5th Bus Cycle). RDa and RDb are the output data. /ADV fixed LOW or toggle HIGH LOW HIGH. 74 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X Figure 9-3. Mode Register Setting Timing Chart (Synchronous Timing) CLK (Input) Address (Input) *A High-Z *A High-Z *A High-Z *A High-Z *A High-Z Don't care High-Z /ADV (Input) /CE1 (Input) /OE (Input) /WE (Output) /LB, /UB (Input) DQ (Input/Output) High-Z RDa High-Z Don't care High-Z Don't care High-Z Code1 High-Z Code2 High-Z RDb High-Z Caution Refer to 8. Synchronous Read/Write specification. Remarks 1. 2. 3. *A means the highest address (7FFFFFH). For the data of Code1 and Code2, refer to Table 5-1. Mode Register Definition (4th Bus Cycle) and Table 5-2. Mode Register Definition (5th Bus Cycle). RDa and RDb are the output data. Preliminary Data Sheet M17507EJ2V0DS 75 PD46128512-X Figure 9-4. Mode Register Setting Flow Chart Start No Read Operation Address = 7FFFFFH toggled the /CE1 and /OE Yes Write Operation Address = 7FFFFFH toggled the /CE1 Yes No No Write Operation Address = 7FFFFFH toggled the /CE1 Yes Write Operation Address = 7FFFFFH toggled the /CE1 Yes No No Mode Register Setting Exit Write Data = Code 1 Note1 Yes Write Operation Address = 7FFFFFH toggled the /CE1 Yes No No Write Data = Code 2 Note2 Yes Read Operation Address = Don't Care toggled the /CE1 and /OE End Re-setup the mode register Notes 1. 2. Refer to Table 5-1. Refer to Table 5-2. 76 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X 10. Standby Mode Timing Chart Figure 10-1. Standby Mode 2 Entry / Exit Timing Chart (Asynchronous Mode) CE2 (Input) tCHML tMHCL /CE1 (Input) Standby Mode 1 Standby Mode 2 Figure 10-2. Standby Mode 2 Entry / Exit Timing Chart (Synchronous Mode) CLK (Input) tCE2S CE2 (Input) tCES tMHCL tCES /CE1 (Input) Standby Mode 1 Standby Mode 2 Standby Mode 2 Entry / Exit Parameter Standby mode 2 entry /CE1 HIGH to CE2 LOW Standby mode 2 exit to normal operation CE2 HIGH to /CE1 LOW Symbol tCHML tMHCL MIN. 0 30 300 /CE1 = HIGH setup time to CLK CE2 = LOW hold time to CLK tCES tCE2S 5 1 MAX. Unit ns ns 1 2 Note s ns ns Notes 1. 2. This is the time it takes to return to normal operation from Standby Mode 2 (data hold: 32M bits / 16M bits / 8M bits). This is the time it takes to return to normal operation from Standby Mode 2 (data not held). Preliminary Data Sheet M17507EJ2V0DS 77 PD46128512-X 11. Package Drawing The following is a package drawing of package sample. 93-PIN TAPE FBGA (12x9) E wSB ZD ZE B A 10 9 8 7 6 5 4 3 2 1 PNM L K J H G F E D C B A INDEX MARK D wSA A y1 S A2 S ITEM D E w e A A1 A2 MILLIMETERS 9.00.1 12.00.1 0.2 0.8 1.30.1 0.160.05 1.14 0.400.05 0.08 0.1 0.2 0.9 0.8 P93F9-80-CR2 y S e A1 S AB b x y y1 ZD ZE b x M 78 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X 12. Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the PD46128512-X package sample. Type of Surface Mount Device PD46128512F9-CR2 : 93-pin TAPE FBGA (12x9) Preliminary Data Sheet M17507EJ2V0DS 79 PD46128512-X Revision History Edition/ Date This edition 2nd edition/ Sep. 2005 p.14 p.14 p.6 Page Previous edition p.6 Modification Burst Operation Addition Modification 3. Page Read Operation 3.1 Features of Page Read Operation p.17 p.17 Modification 4.4 Single Write 4.5 /WE Control p.18 p.18 Modification 4.6 Burst Read Suspend/ Resume p.19 p.19 Modification 4.7 Burst Write Suspend/ Resume p.22 p.23 p.22 p.23 Modification 4.10.1 Feature of /WAIT output Addition Text has been modified. Text has been modified. Text has been modified. Text has been modified. Text has been modified. Notes 3 and 8 have been modified. Note 10 has been added. Text has been modified. Note has been modified. Type of revision Location Description (Previous edition This edition) Figure 4-8. Read /WAIT Output Text has been added. (/CE1 = LOW, /ADV = HIGH LOW) p.25 p.26 p.25 p.26 Addition Addition Table 4-1. Burst Sequence Table 4-2. Dummy Wait Cycles and Read Latency Remark 2 has been added. "(Write Latency = n-1)" has been added in parameter of table. Remark has been modified. Modification p.27 p.27 Addition 4.11 Reset Function from Synchronous Burst Mode to Asynchronous Page Mode p.28 p.28 Modification 5.1 Mode Register Setting Method Addition 5.2 Cautions for Setting Mode Register p.32 p.32 Modification 5. 12 Caution for Timing Chart of Setting Mode p.42 p.42 Addition Figure 7-10. Asynchronous Page Read Cycle Timing Chart pp.43-56 pp.43-56 Modification Each Figures p.57 p.57 Modification 8. Synchronous AC Specification, Timing Chart p.77 p.77 Modification Figure 10-2. Standby Mode 2 Entry / Exit Timing Chart (Synchronous Mode) "Refer to Figure 2-1. Standby Mode State Machine." has been added. "read a specific address" "read any address" "except page mode (M = 1)" has been added. Text has been modified. Cautions 4 and 5 have been added. Remark has been modified. Title has been modified. Title has been modified. 80 Preliminary Data Sheet M17507EJ2V0DS PD46128512-X NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Preliminary Data Sheet M17507EJ2V0DS 81 PD46128512-X * The information in this document is current as of September, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 |
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